The present invention generally relates to semiconductor memory devices. More particularly, the present invention relates to redundancy circuits within semiconductor memory devices.
Random access memory (RAM) is a component used within electronic systems to store data for use by other components within the system. Dynamic RAM (DRAM) is a type of RAM which uses a capacitor-type storage and requires periodic refreshing in order to maintain the data stored within the DRAM. Static RAM (SRAM) is another type of RAM which retains the information stored within the SRAM as long as power is applied. SRAM does not require periodic refreshing in order to maintain the stored data. Synchronous DRAM (SDRAM) operates within a synchronous memory system such that input and output signals are synchronized to an active edge of a system clock.
RAM is generally organized within the system into addressable blocks, each containing a predetermined number of memory cells. Each memory cell within a RAM represents a bit of information. The memory cells are organized into rows and columns. Each row of memory cells forms a word. Each memory cell within a row is coupled to the same wordline which is used to activate the memory cells within the row. The memory cells within each column of a block of memory are also each coupled to a pair of bitlines. These bitlines are also coupled to local input/output (LIO) lines. These local input/output lines are used to read data from an activated memory array or write data to an activated memory array. The pair of bitlines includes a bitline and an inverse bitline. A memory cell is therefore accessed by activating the appropriate wordline and pair of bitlines.
An address bus and next address bus are used to access specified memory cells within a memory array. The information on the address bus or next address bus is latched onto the wordline and bitline used for accessing data within the memory array. The next address bus is used when operating in a burst cycle mode to transfer large blocks of data. Addressing information is split into row and column address information which is decoded by individual row and address decoders to decrease access time. Burst cycle mode is used to transfer large blocks of data. Typically, in a burst cycle mode the memory array is divided into even and odd blocks with the address bus used to access the even block and the next address bus used to access the odd block. The next address is typically generated by automatically incrementing the address from the address bus. In this way, data may be transferred more rapidly.
Memory circuits are fabricated on wafers. Wafer yield is defined as the ratio of non-defective chips to the number of total chips fabricated on a given wafer. In general, as integration density in semiconductor memory devices increases, the likelihood of defective cells in any one memory array also increases. Therefore, the higher the integration density of chips fabricated on a given wafer, the lower the wafer yield.
It has been determined that an effective method for increasing wafer yield is to use redundant memory to replace defective memory. Redundant memory includes redundant memory cells which are configured in rows and/or columns and are used to replace rows and/or columns of the main memory array which are found to have one or more defective memory cells.
One problem which exists with the use of redundant memory circuits as substitutes for main memory circuits is access time. The column address is typically provided simultaneously to both a regular column address decoder and a redundant column address decoder. The redundant column address decoder is programmed with the addresses of defective columns. The redundant column address decoder decodes the column address and determines if the column address is programmed within the redundant memory array. If the column address corresponds to an address programmed into the redundant column address decoder, then the redundant column address decoder disables the regular column address decoder and initiates access to the redundant memory array. Otherwise, if the column address is not included within the redundant memory array, then the regular column address decoder is not disabled and the memory access is performed in the main memory array. The regular column address decoder must wait for the output of the redundant column address decoder to be valid before proceeding with the memory access. This waiting causes delays and extends the time necessary for each memory access operation.
A block diagram of a conventional redundancy address decoding circuit which requires a delay in the decoding scheme is illustrated in FIG. 1. Initially, either the information on the address bus 10 or the information on the next address bus 20 is latched by a latch 30 onto the column address bus 40. The information on the address bus 10 is latched by the latch 30 when beginning at a new column address. When the column address enable signal (CAEN) 15 is activated to a logical high voltage level, the information on the address bus 10 is passed through the transistor 13 and latched by the latch 30 onto the column address bus 40. The information on the next address bus 20 is latched by the latch 30 onto the column address bus 40 for the next address in a burst cycle mode. When the next address in a burst cycle is needed, the column address counter signal (CACTR) 25 is activated to a logical high voltage level, enabling the next address information from the next address bus 20 to be passed through the transistor 12 and latched by the latch 30 onto the column address bus 40.
The information latched by the latch 30 onto the column address bus 40 is provided as an input to both a regular column decoder 50 and a redundant column decoder 60. The regular column decoder 50 and the redundant column decoder 60 are arranged in parallel to decode the address information on the column address bus 40. If the redundant column decoder 60 detects an address within a corresponding redundant column memory array 100, then the redundant column decoder 60 sends a disabling signal to the regular column decoder 50 which disables the regular column pathway. If the redundant column decoder 60 detects an address within the redundant column memory array 100, then the redundant column decoder 60 also provides the decoded redundancy address information to a redundancy column select circuit 90. The redundancy column select circuit 90 then provides this information to circuitry (not shown) to complete the memory access operation, either read or write, within the redundancy column memory array 100. If the redundant column decoder 60 does not decode an address within the redundancy column array 100, then the regular column pathway is not disabled and the regular column decoder 50 then provides the decoded address information to a regular column select circuit 80. The regular column select circuit 80 then provides this information to circuitry (not shown) to complete the memory access operation, either read or write, within the corresponding regular column memory array 110.
Accordingly, in such a configuration, in order to ensure that the regular column pathway is properly disabled when the column address is within the redundant memory array 100, the output from the regular column decoder 50 is delayed until the disable output 70 from the redundant column decoder 60 is valid. This delay is included within each memory access operation. One previous method for resolving this delay was to load both regular and redundant column activate information and data onto both the regular local I/O signal lines and the redundant local I/O signal lines and then select the appropriate local I/O signal lines using the disable output of the redundant column decoder.
A block diagram of a prior art technique for avoiding delay during memory access operations is illustrated in FIG. 2. Initially, either the information on the address bus 200 or the information on the next address bus 210 is latched by a latch 230 onto the column address bus 240. The information on the address bus 200 is latched by the latch 230 when beginning at a new column address. The column address enable signal (CAEN) 215 is activated to a logical high voltage level, enabling the information on the address bus 200 to pass through the transistor 212 and to be latched by the latch 230 onto the column address bus 240. The information on the next address bus 210 is latched by the latch 230 for the next address in a burst cycle mode. When the next address in a burst cycle is needed, the column address counter signal (CACTR) 225 is activated to a logical high voltage level, enabling the next address information from the next address bus 210 to pass through the transistor 213 to the latch 230. The next address information is then latched by the latch 230 onto the column address bus 240.
A regular column decoder 250 and a redundant column decoder 260 are arranged in parallel to decode the address information on the column address bus 240. The regular column decoder 250 is coupled to a regular column address select circuit 280 and the redundant column decoder is coupled to a redundant column address select circuit 290. The regular column decoder outputs the regular column address corresponding to the current addressing information to the regular column address select circuit 280 which instructs drivers (not shown) to perform the memory access operation within the regular memory array 300 utilizing the local I/O signal lines 310. If the redundant column decoder 260 detects an address within the redundant column memory array 320, then the redundant column decoder 260 outputs the decoded redundancy address information to the redundancy column address select circuit 290 which instructs memory drivers (not shown) to perform the memory access operation within the redundancy column memory array 320 utilizing the redundant local I/O signal lines 325. Both the local I/O signal lines 310 and the redundant local I/O signal lines 325 are coupled to a multiplexer 330. The local I/O signal lines 310 are coupled to an input A of the multiplexer 330, while the redundant local I/O signal lines 325 are coupled to an input B of the multiplexer 330. The signal REDUN 350 is output from the redundant column decoder 260 and provided as the control input to the multiplexer 330, to control which of the I/O signal lines 310 or the redundant local I/O signal lines 325 are selected by the multiplexer 330. If the redundant column decoder 260 detects an address within the redundancy column array 320, the REDUN signal 350 is raised to a logical high voltage level by the redundant column decoder 260 and the data on the redundancy local I/O signal lines 325 at the input B to is selected by the multiplexer 330. Otherwise, if the redundant column decoder 260 does not detect an address within the redundancy column array 320, the signal REDUN is pulled to a logical low voltage level and the data on the local I/O signal lines 310 at the input A is selected by the multiplexer 330. This solution will speed up access time during memory access operations but requires significant additional layout at the cost of additional space and complexity. What is needed is an improved circuit for decoding a column address and controlling access to regular and redundancy column memory cells.
A look ahead column redundancy circuit provides high speed memory access to both regular memory arrays and redundant memory arrays. In the preferred embodiment of the present invention, the information on both the address bus and the information on the next address bus are decoded by redundant column decoders in parallel. The decoded information from the redundant column decoders is then provided to a redundancy column pathway as the addressing information from the address bus and the next address bus is provided to a main column pathway through a latch. The information on the address bus is latched when beginning at a new column address. The information on the next address bus is latched for the next column address when operating in a burst cycle mode. The main column pathway preferably includes a main column decoder and a main column select circuit. A disable signal is also activated by the redundant column decoders if the addressing information for a current memory access operation corresponds to an address within the redundant memory array. When activated, the disable signal disables the main column select circuit within the main column pathway. If the addressing information for a current memory access operation does not correspond to an address within the redundant memory array, then the memory access operation is performed within the main memory array without any additional delays. Since the decoding is performed before the information is latched onto the column address bus, the proper pathway is selected without the need for any additional delay.
In one aspect of the present invention, an apparatus for accessing a memory structure including a main memory array and a redundant memory array comprises an address bus for carrying addressing information for a current memory access operation, a main column pathway including a main column decoder for decoding addressing information and a main select circuit for selecting appropriate groups of memory cells within the main memory array for a current memory access operation and a redundant column pathway including a redundant column decoder for decoding addressing information and a redundant select circuit for selecting appropriate groups of memory cells within the redundant memory array for a current memory access operation if the current memory access operation is accessing memory cells within the redundant memory array, wherein the redundant column pathway is selected if the current memory access operation is accessing memory cells within the redundant memory array. The redundant column decoder disables the main select circuit if the current memory access operation is accessing memory cells within the redundant memory array. The redundant column decoder is provided the addressing information before the main column pathway. The main column pathway is provided the addressing information and the redundant select circuit is provided decoded redundant addressing information from the redundant column decoder in response to a control signal. The groups of memory cells are columns.
In another aspect of the present invention, a method of completing memory access operations within a memory structure including a main memory array and a redundant memory array, comprises the steps of determining from addressing information for a current memory access operation if the addressing information represents an address included within the redundant memory array, decoding a redundant address within the redundant memory array, if the addressing information represents an address included within the redundant memory array, providing the addressing information for the current memory access operation to a main column pathway and providing the redundant address to a redundant column pathway in response to a first control signal, decoding a main address within the main memory array corresponding to the addressing information; activating a group of main memory cells within the main memory array corresponding to the main address and selecting the redundant column pathway if the addressing information represents an address included within the redundant memory array. The method further includes the step of disabling the step of activating a group of main memory cells, if the addressing information represents an address included within the redundant memory array. The method further includes the step of activating a group of redundant memory cells within the redundant memory array, if the addressing information represents an address included within the redundant memory array. The step of decoding a redundant address is completed before the step of providing the addressing information. The groups of main memory cells are columns within the main memory array. The groups of redundant memory cells are columns within the redundant memory array.
In yet another aspect of the present invention, an apparatus for controlling access to a memory structure including a regular memory array and a redundancy memory array comprises an address bus for carrying addressing information for a current memory access operation, a first redundancy column decoder coupled to the address bus for decoding the addressing information, the first redundancy column decoder including a first output for providing a first decoded redundancy address and a second output for providing a disable signal, a first pass through circuit coupled to the address bus for passing through the addressing information in response to a first control signal, a first latching circuit coupled to the first pass through circuit for latching the addressing information which has passed through the first pass through circuit, a regular column decoder circuit coupled to the first latching circuit for decoding the addressing information and providing a decoded regular address, a second pass through circuit coupled to the first output of the first redundancy column decoder for passing through the first decoded redundancy address in response to the first control signal, a second latching circuit coupled to the second pass through circuit for latching the first decoded redundancy address from the first output of the first redundancy column decoder which has passed through the second pass through circuit, a regular column select circuit coupled to the regular column decoder to receive the decoded regular address and to select a corresponding regular column address within the regular memory array, wherein the regular column select circuit is also coupled to receive the disable signal from the second output of the first redundancy column decoder for disabling the regular column select circuit if the addressing information corresponds to an address within the redundancy memory array and a redundancy column select circuit coupled to the second latching circuit to receive the first decoded redundancy address and to select a corresponding redundant column address within the redundancy memory array, if the addressing information corresponds to an address within the redundancy memory array. The first redundancy column decoder is provided the addressing information before the first latching circuit. The first control signal is a column address enable signal. The apparatus further includes a next address bus for carrying next addressing information for a next memory access operation, a second redundancy column decoder coupled to the next address bus for decoding the next addressing information, the second redundancy column decoder including a third output for providing a second decoded redundancy address and a fourth output for providing the disable signal, a third pass through circuit coupled to the next address bus for passing through the next addressing information in response to a second control signal, wherein the third pass through circuit is also coupled to pass the next addressing information through to the first latching circuit and a fourth pass through circuit coupled to the third output of the second redundancy column decoder for passing through the second decoded redundancy address in response to the second control signal, wherein the fourth pass through circuit is also coupled to pass the second decoded redundancy address through to the second latching circuit. The first and second column decoders are provided the addressing information and the next addressing information before the first latching circuit. The second control signal is a column address counter signal.